Status

Last update:

In sum, we expect:

  • dataflow, instruction ordering and automatic abstractions to be completed in 2024/Q1 to 2024/Q2
  • statical analysis, compiled flexibility and the IDE to take more time, probably at least half a year each
  • minor works to take an additional 6-12 months

This leaves us with an ETA in 2026-2027.

The project has started being actively implemented after years of pure designing. The first step, creating Graph-to-LLVM bindings, is done. The dataflow abstraction is in late design phase, soon to be implemented.

However, we are still far from a usable implementation as many major points are not yet implemented (see list below).

We expect completion of the first specifications and dataflow abstraction within the next weeks. Instruction ordering and automatic abstractions will follow soon after, as they depend on the dataflow abstraction.

Automatic parallelization and inline assembly may not be implemented sequentially, but at a later point, because they are not necessities.

The effort required to implement statical analysis is difficult to estimate. Compiled flexibility and the IDE will take relatively much time to implement. Higher level abstractions are not designed yet, but will probably not take significantly long.

In sum, we expect:

  • dataflow, instruction ordering and automatic abstractions to be completed in 2024/Q1 to 2024/Q2
  • statical analysis, compiled flexibility and the IDE to take more time, probably at least half a year each
  • minor works to take an additional 6-12 months

This leaves us with an ETA in 2026-2027.

Overview of missing points:

  • Specifications as documentation and source for ORMs for graphs (for type-safe graph encoding/decoding)
  • Dataflow abstraction
  • Instruction ordering abstraction and implementation
  • Abstract over control flow in dataflow abstraction (basic blocks and terminator instructions)
  • Automatic abstractions
  • Automatic parallelization (may be skipped and implemented later)
  • Memory allocation (will delegate to malloc by default in environments with operating systems)
  • LLVM Inline assembly / native ISA targets (x86_64/ARM) (may be skipped and implemented later)
  • Statical analysis
  • Compiled flexibility
  • Reactivity
  • Other higher abstractions (passes)
  • Graph IDE & explicit abstractions